Increased miniaturization is an important goal in today's rapidly advancing semiconductor manufacturing industry. There is a push to reduce device feature sizes and to increase integration levels within a device as well as to reduce the size of the semiconductor chips themselves. CUP (circuit under pad) technologies have enabled the placement of bond pads anywhere on the semiconductor chip and also enabled additional bond pads to be packed in close proximity. While the increase in integration levels and advances in miniaturization provide semiconductor chips that can store more data, perform more functions and are smaller in size, an undesirable by-product of such a decrease in semiconductor chip size is that the bond pads for connecting the semiconductor chip to external features become smaller and more tightly packed. The ability to continue to shrink the size of the semiconductor chip is now limited by the constraints of the bonding processes used to package the semiconductor chips, i.e. to couple the bond pads to external components such as packaging elements, in both wire bond and flip chip processing. Both wire bonding and flip chip processing require a minimum bond pad size and a minimum spacing between the bond pads to bond a wire to or couple a solder ball to the bond pad.
There is therefore a tradeoff between reducing chip size to increase integration levels and providing bond pads that are large enough and spaced far apart enough to enable them to be coupled to external components using commercially available bonding processes used in assembling and packaging the semiconductor chips. The present invention addresses this shortcoming of conventional practices.